View EVAL-AD7887CB4_6532746.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2.7 v to 5.25 v, micropower, 2-channel, 125 ksps, 12-bit adc in 8-lead msop ad7887 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features specified for v dd of 2.7 v to 5.25 v flexible power/throughput rate management shutdown mode: 1 a max one or two single-ended inputs serial interface: spi?/qspi?/microwire?/dsp compatible 8-lead narrow soic and msop packages applications battery-powered systems (personal digital assistants, medical instruments, mobile communications) instrumentation and control systems high speed modems functional block diagram sar + adc control logic gnd ain0 sclk dout din v dd ad7887 cs t/h i/p mux buf charge redistribution dac comp a in1/ v ref ain1/v ref software control latch 2.5v ref sport 0 6191-001 figure 1. general description the ad7887 is a high speed, low power, 12-bit analog-to-digital converter (adc) that operates from a single 2.7 v to 5.25 v power supply. the ad7887 is capable of 125 ksps throughput rate. the input track-and-hold acquires a signal in 500 ns and features a single-ended sampling scheme. the output coding for the ad7887 is straight binary, and the part is capable of converting full power signals of up to 2.5 mhz. the ad7887 can be configured for either dual- or single-channel operation via the on-chip control register. there is a default single-channel mode that allows the ad7887 to be operated as a read-only adc. in single-channel operation, there is one analog input (ain0) and the ain1/v ref pin assumes its v ref function. this v ref pin allows the user access to the parts internal 2.5 v reference, or the v ref pin can be overdriven by an external reference to provide the reference voltage for the part. this external reference voltage has a range of 2.5 v to v dd . the analog input range on ain0 is 0 to v ref . in dual-channel operation, the ain1/v ref pin assumes its ain1 function, providing a second analog input channel. in this case, the reference voltage for the part is provided via the v dd pin. as a result, the input voltage range on both the ain0 and ain1 inputs is 0 to v dd . cmos construction ensures low power dissipation of typically 2 mw for normal operation and 3 w in power-down mode. the part is available in an 8-lead, 0.15-inch-wide narrow body soic and an 8-lead msop package. product highlights 1. smallest 12-bit dual-/single-channel adc; 8-lead msop package. 2. lowest power 12-bit dual-/single-channel adc. 3. flexible power management options, including automatic power-down after conversion. 4. read-only adc capability. 5. analog input range from 0 v to v ref . 6. versatile serial input/output port (spi/qspi/microwire/ dsp compatible).
ad7887 rev. d | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 8 ? terminology ...................................................................................... 9 ? control register .............................................................................. 10 ? theory of operation ...................................................................... 11 ? circuit information .................................................................... 11 ? converter operation .................................................................. 11 ? adc transfer function ............................................................. 11 ? typical connection diagram ................................................... 11 ? analog input ............................................................................... 12 ? power-down options ................................................................ 13 ? power vs. throughput rate ....................................................... 13 ? modes of operation ................................................................... 13 ? serial interface ............................................................................ 17 ? microprocessor interfacing ....................................................... 18 ? application hints ....................................................................... 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 21 ? revision history 2/09rev. c to rev. d c hanges to ordering guide .......................................................... 21 9/06rev. b to rev. c updated format .................................................................. universal change to absolute maximum ratings ......................................... 6 additions to pin configurations .................................................... 7 added table 7 .................................................................................. 18 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21
ad7887 rev. d | page 3 of 24 specifications v dd = 2.7 v to 5.25 v, v ref = 2.5 v, external/internal reference unless otherwise noted, f sclk = 2 mhz, t a = t min to t max , unless otherwise noted. table 1. parameter a version 1 b version 1 unit test conditions/comments dynamic performance signal to noise + distortion ratio (snr) 2 , 3 71 71 db typ f in = 10 khz sine wave, f sample = 125 ksps total harmonic distortion (thd) 2 ?80 ?80 db typ f in = 10 khz sine wave, f sample = 125 ksps peak harmonic or spurious noise 2 C80 ?80 db typ f in = 10 khz sine wave, f sample = 125 ksps intermodulation distortion (imd) 2 second-order terms ?80 ?80 db typ fa = 9.983 khz, fb = 10.05 khz, f sample = 125 ksps third-order terms ?80 ?80 db typ fa = 9.983 khz, fb = 10.05 khz, f sample = 125 ksps channel-to-channel isolation 2 ?80 ?80 db typ f in = 25 khz full-power bandwidth 2.5 2.5 mhz typ @ 3 db dc accuracy any channel resolution 12 12 bits integral nonlinearity 2 2 1 lsb max differential nonlinearity 2 2 1 lsb max guaranteed no missing codes to 11 bits (a grade) offset error 2 3 3 lsb max v dd = 5 v, dual-channel mode 4 4 lsb max v dd = 3 v, dual-channel mode 6 6 lsb typ single-channel mode offset error match 2 0.5 0.5 lsb max gain error 2 2 2 lsb max dual-channel mode 1 1 lsb max single-channel mode, external reference 6 6 lsb typ single-channel mode, internal reference gain error match 2 2 2 lsb max analog input input voltage ranges 0 to v ref 0 to v ref v leakage current 5 5 a max input capacitance 20 20 pf typ reference input/output ref in input voltage range 2.5/v dd 2.5/v dd v min/max functional from 1.2 v input impedance 10 10 k typ very high impedance if internal reference disabled ref out output voltage 2.45/2.55 2.45/2.55 v min/max ref out temperature coefficient 50 50 ppm/c typ logic inputs input high voltage, v inh 2.4 2.4 v min v dd = 4.75 v to 5.25 v 2.1 2.1 v min v dd = 2.7 v to 3.6 v input low voltage, v inl 0.8 0.8 v max v dd = 2.7 v to 5.25 v input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 4 10 10 pf max logic outputs output high voltage, v oh i source = 200 a v dd ? 0.5 v dd ? 0.5 v min v dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 0.4 v max i sink = 200 a floating-state leakage current 1 1 a max floating-state output capacitance 5 10 10 pf max output coding straight (natural) binary
ad7887 rev. d | page 4 of 24 parameter a version 1 b version 1 unit test conditions/comments conversion rate throughput time 16 16 sclk cycles conversion time plus acquisition time is 125 ksps, with 2 mhz clock track/hold acquisition time 2 1.5 1.5 sclk cycles conversion time 14.5 14.5 sclk cycles 7.25 s (2 mhz clock) power requirements v dd +2.7/+5.25 +2.7/+5.25 v min/max i dd normal mode 5 (mode 2) static 700 700 a max operational (f sample = 125 ksps) 850 850 a typ internal reference enabled 700 700 a typ internal reference disabled using standby mode (mode 4) 450 450 a typ f sample = 50 ksps using shutdown mode (modes 1, 3) 120 120 a typ f sample = 10 ksps 12 12 a typ f sample = 1 ksps standby mode 6 210 210 a max v dd = 2.7 v to 5.25 v shutdown mode 6 1 1 a max v dd = 2.7 v to 3.6 v 2 2 a max v dd = 4.75 v to 5.25 v normal mode power dissipation 3.5 3.5 mw max v dd = 5 v 2.1 2.1 mw max v dd = 3 v shutdown power dissipation 5 5 w max v dd = 5 v 3 3 w max v dd = 3 v standby power dissipation 1.05 1.05 mw max v dd = 5 v 630 630 w max v dd = 3 v 1 temperature range for a and b versions is ? 40c to +125c. 2 see the terminology section. 3 snr calculation includes dist ortion and noise components. 4 sample tested at +25c to ensure compliance. 5 all digital inputs at gnd except cs at v dd . no load on the digital outputs. analog inputs at gnd. 6 sclk at gnd when sclk off. all digital inputs at gnd except for cs at v dd . no load on the digital outputs. analog inputs at gnd.
ad7887 rev. d | page 5 of 24 timing specifications 1 table 2. limit at t min , t max (a, b versions) parameter 4.75 v to 5.25 v 2.7 v to 3.6 v unit description f sclk 2 2 2 mhz max t convert 14.5 t sclk 14.5 t sclk t acq 1.5 t sclk 1.5 t sclk throughput time = t convert + t acq = 16 t sclk t 1 10 10 ns min cs to sclk setup time t 2 3 30 60 ns max delay from cs until dout three-state disabled t 3 3 75 100 ns max data access time after sclk falling edge t 4 20 20 ns min data setup time prior to sclk rising edge t 5 20 20 ns min data valid to sclk hold time t 6 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 7 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 8 4 80 80 ns max cs rising edge to dout high impedance t 9 5 5 s typ power-up time from shutdown 1 sample tested at 25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 mark/space ratio for the sc lk input is 40/60 to 60/40. 3 measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.8 v or 2.0 v. 4 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteri stics is the true bus relinquish time of the part and is in dependent of the bus loading. 200a i ol 200a i oh 1.6v to o utput pin c l 50pf 06191-002 figure 2. load circuit for digita l output timing specifications
ad7887 rev. d | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to agnd ?0.3 v to +7 v analog input voltage to agnd ?0.3 v to v dd + 0.3 v digital input voltage to agnd ?0.3 v to v dd + 0.3 v digital output voltage to agnd ?0.3 v to v dd + 0.3 v ref in /ref out to agnd ?0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial temperature range a, b versions ?40c to +125c storage temperature range ?65c to +150c junction temperature +150c soic or msop package power dissipation 450 mw ja thermal impedance 157c/w (soic) 205.9c/w (msop) jc thermal impedance 56c/w (soic) 43.74c/w (msop) lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c pb-free temperature, soldering reflow 260(0)c esd 4 kv 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7887 rev. d | page 7 of 24 pin configurations and function descriptions cs 1 v dd 2 gnd 3 ain1/v ref 4 sclk 8 dout 7 din 6 ain0 5 ad7887 top view (not to scale) 06191-003 cs 1 v dd 2 gnd 3 ain1/v ref 4 sclk 8 dout 7 din 6 ain0 5 ad7887 top view (not to scale) 06191-004 figure 3. soic_n pin configuration figure 4. msop pin configuration table 4. pin function descriptions pin no. mnemonic description 1 cs chip select. active low logic input. this input provides the dual function of initiating conversions on the ad7887 and also frames the serial data transfer. wh en the ad7887 operates in its default mode, the cs pin also acts as the shutdown pin such that with the cs pin high, the ad7887 is in its power-down mode. 2 v dd power supply input. the v dd range for the ad7887 is from 2.7 v to 5.25 v. when the ad7887 is configured for two-channel operation, this pin also provides the reference source for the part. 3 gnd ground pin. this pin is the ground reference point for a ll circuitry on the ad7887. in systems with separate agnd and dgnd planes, these planes should be tied together as close as possible to this gnd pin. where this is not possible, this gnd pin should connect to the agnd plane. 4 ain1/v ref analog input 1/voltage reference input. in single-chann el mode, this pin becomes the reference input/output. in this case, the user can either access the internal 2. 5 v reference or overdrive the internal reference with the voltage applied to this pin. the reference voltage range for an externally applied reference is 1.2 v to v dd . in two- channel mode, this pin provides the second analog inp ut channel, ain1. the input voltage range on ain1 is 0 to v dd . 5 ain0 analog input 0. in single-channel mode, this is the analog input and the input voltage range is 0 to v ref . in dual- channel mode, it has an analog input range of 0 to v dd . 6 din data in. logic input. data to be written to the ad7887s cont rol register is provided on this input and clocked into the register on the rising edge of sclk (see the control register section). the ad7887 can be operated as a single-channel, read-only adc by tying the din line permanently to gnd. 7 dout data out. logic output. the conversion result from the ad7887 is provided on this outp ut as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream consists of four leading zeros followed by the 12 bits of conversion data, which is provided msb first. 8 sclk serial clock. logic input. sclk provides the serial clock fo r accessing data from the part and writing serial data to the control register. this clock input is also used as the clock source for the ad7887s conversion process.
ad7887 rev. d | page 8 of 24 typical performance characteristics 6.103516 0 12.20703 18.31055 24.41406 30.51758 36.62109 42.72461 48.82813 54.93164 61.03516 ?110 0 ?10 ?30 ?50 ?70 ?90 4096 point fft sampling 125ksps f in = 10khz snr = 71db 06191-005 input frequency (khz) ?93 2.65 64.15 psrr (db) 12.85 v dd = 5.5v/2.7v 100mv p-p sine wave on v dd ref in = 2.488v ext reference 23.15 33.65 ?91 ?89 ?87 ?85 ?83 ?81 ?79 ?77 ? 75 43.85 54.35 06191-007 figure 5. dynamic performance figure 7. psrr vs. frequency input frequency (khz) 71.0 0.15 42.14 sn r (db) 73.0 72.5 72.0 71.5 31.59 10.89 v dd = 5v 5v ext reference 21.14 0 6191-006 figure 6. snr vs. input frequency
ad7887 rev. d | page 9 of 24 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point ? lsb below the first code transition, and full scale, a point ? lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, agnd + 0.5 lsb. offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (that is, v ref ? 1.5 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two channels. track/hold acquisition time the track/hold amplifier returns to track mode at the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of a conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fun- damental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal to (noise + distortion) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7887, it is defined as 1 2 6 2 5 2 4 2 3 2 2 log20)db( v vvvvv thd ++++ = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second- order terms include (fa + fb) and (fa ? fb), and the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). the ad7887 is tested using the ccif standard in which two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale 25 khz sine wave signal to the nonselected input channel and determining how much that signal is attenuated in the selected channel. the figure given is the worst case across both channels for the ad7887. power supply rejection (psr) variations in power supply affect the full-scale transition, but not the converters linearity. psr is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. see figure 7 . psrr is defined as the ratio of the power in the adc output at frequency f to the power of a full-scale sine wave applied to the adc of frequency f s : psrr (db) = 10 log(pf / pfs ) where pf is the power at frequency f in adc output and pfs is the power at frequency f s in adc full-scale input.
ad7887 rev. d | page 10 of 24 control register the control register on the ad7887 is an 8-bit, write-only register. data is loaded from the din pin of the ad7887 on the risin g edge of sclk. the data is transferred on the din line at the same time as the conversion result is read from the part. this requires 16 serial clocks for every data transfer. only the information provided on the first eight rising clock edges after cs falling edge is loaded to the control register. msb denotes the first bit in the data stream. the bit functions are outlined in . the contents of the control register on power up is all 0s. table 5 msb dontc zero ref sin/dual ch zero pm1 pm0 table 5. control register bit mnemonic comment 7 dontc dont care. the value written to this bit of the control regist er is a dont care, that is, it doesnt matter if the bit is 0 or 1. 6 zero a zero must be written to this bit to ensure correct operation of the ad7887. 5 ref reference bit. with a 0 in this bit, the on-chip reference is enabled. with a 1 in this bit, the on-chip reference is disabled. 4 sin/dual single/dual bit. this bit determines whether the ad 7887 operates in single-channel or dual-channel mode. a 0 in this bit selects single-channel operation and the ain1/v ref pin assumes its v ref function. a 1 in this bit selects dual-channel mode, with the reference voltage for the adc internally connected to v dd and the ain1/v ref pin assuming its ain1 function as the second analog input channel. to obtain best performance from the ad7887, the internal reference should be disabled when operating in the dual-channel mode, that is, ref = 1. 3 ch channel bit. when the part is selected for dual-channe l mode, this bit determines which channel is converted for the next conversion. a 0 in this bit selects the ain0 input, and a 1 in this bit selects the ain1 input. in single- channel mode, this bit should always be 0. 2 zero a 0 must be written to this bit to ensure correct operation of the ad7887. 1, 0 pm1, pm0 power management bits. these two bits de code the mode of operation of the ad7887 as described in table 6 . table 6. power management options pm1 pm0 mode 0 0 mode 1. in this mode, the ad7887 enters shutdown if the cs input is 1 and is in full power mode when cs is 0. thus the part comes out of shutdown on the falling edge of cs and enters shutdown on the rising edge of cs . 0 1 mode 2. in this mode, the ad7887 is always fully powered up, regardless of the status of any of the logic inputs. 1 0 mode 3. in this mode, the ad7887 automatically enters shutdown mode at the end of each conversion, regardless of the state of cs . 1 1 mode 4. in this standby mode, portions of the ad7887 are powered down but the on-chip reference voltage remains powered up. this mode is similar to mode 3, b ut allows the part to power up much faster. the ref bit should be 0 to ensure that the on-chip reference is enabled.
ad7887 rev. d | page 11 of 24 theory of operation circuit information the ad7887 is a fast, low power, 12-bit, single-supply, single- channel/dual-channel adc. the part can be operated from a 3 v (2.7 v to 3.6 v) supply or from a 5 v (4.75 v to 5.25 v) supply. when operated from either a 5 v or 3 v supply, the ad7887 is capable of throughput rates of 125 ksps when provided with a 2 mhz clock. the ad7887 provides the user with an on-chip, track/hold analog-to-digital converter reference and a serial interface housed in an 8-lead package. the serial clock input accesses data from the part and provides the clock source for the successive approximation adc. the part can be configured for single- channel or dual-channel operation. when configured as a single-channel part, the analog input range is 0 to v ref (where the externally applied v ref can be between 1.2 v and v dd ). when the ad7887 is configured for two input channels, the input range is determined by internal connections to be 0 to v dd . if single-channel operation is required, the ad7887 can be operated in a read-only mode by tying the din line permanently to gnd. for applications where the user wants to change the mode of operation or wants to operate the ad7887 as a dual- channel adc, the din line can be used to clock data into the parts control register. converter operation the ad7887 is a successive approximation adc built around a charge-redistribution dac. figure 8 and figure 9 show simplified schematics of the adc. figure 8 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on ain. (ref in/ref out)/2 sampling capacitor comparator acquisition phase sw1 a sw2 agnd b a in charge redistribution dac control logic 06191-008 figure 8. adc acquisition phase when the adc starts a conversion (see figure 9 ), sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the control logic and the charge-redistribution dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 10 shows the adc transfer function. (ref in/ref out)/2 sampling capacitor comparator conversion phase sw1 a sw2 agnd b v in charge redistribution dac control logic 06191-009 figure 9. adc conversion phase adc transfer function the output coding of the ad7887 is straight binary. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsb, and so on). the lsb size is v ref /4096. the ideal transfer characteristic for the ad7887 is shown in figure 10. 0v adc code analog input 111 ... 000 011 ... 111 0.5lsb +v ref ? 1.5lsb 1lsb = v ref /4096 111 ... 111 111 ... 110 000 ... 010 000 ... 001 000 ... 000 06191-010 figure 10. transfer characteristic typical connection diagram figure 11 shows a typical connection diagram for the ad7887. the gnd pin is connected to the analog ground plane of the system. the part is in dual-channel mode so v ref is internally connected to a well-decoupled v dd pin to provide an analog input range of 0 v to v dd . the conversion result is output in a 16-bit word with four leading zeros followed by the msb of the 12-bit result. for applications where power consumption is of concern, the automatic power-down at the end of conversion should be used to improve power performance. see the modes of operation section. dout din sclk cs ain1 ain2 gnd 0.1f 10f supply 2.7v to 5.25v serial interface v dd ad7887 0v to v dd input c/p 06191-011 figure 11. typical connection diagram
ad7887 rev. d | page 12 of 24 analog input figure 12 shows an equivalent circuit of the analog input structure of the ad7887. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceed the supply rails by more than 200 mv. exceeding this value causes the diodes to become forward biased and to start conducting into the substrate. the maximum current these diodes can conduct without causing irreversible damage to the part is 20 ma. however, it is worth noting that a small amount of current (1 ma) being conducted into the substrate due to an overvoltage on an unselected channel can cause inaccurate conversions on a selected channel. capacitor c1 in figure 12 is typically about 4 pf and can primarily be attributed to pin capacitance. resistor r1 is a lumped component made up of the on resistance of a multiplexer and a switch. this resistor is typically about 100 . capacitor c2 is the adc sampling capacitor and typically has a capacitance of 20 pf. note that the analog input capacitance seen when in track mode is typically 38 pf, whereas in hold mode it is typically 4 pf. v in v dd d2 r1 c1 4pf conversion phase?switch open track phase?switch closed d1 c2 20pf 06191-012 figure 12. equivalent analog input circuit for ac applications, removing high frequency components from the analog input signal is recommended by use of an rc low-pass filter on the relevant analog input pin. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of op amp is a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases and performance degrades. figure 13 shows a graph of the total harmonic distortion vs. the analog input signal frequency for different source impedances. input frequency (khz) ?90 41.24 51.0 thd (db) 10.89 31.59 21.14 ?85 ?80 ?75 ?70 ? 65 49.86 thd vs. frequency for different source impedances v dd = 5v 5v ext reference r in = 1k ? , c in = 100pf r in = 50 ? , c in = 2.2nf r in = 10 ? , c in = 10nf 0 6191-013 figure 13. thd vs. analog input frequency on-chip reference the ad7887 has an on-chip 2.5 v reference. this reference can be enabled or disabled by clearing or setting the ref bit in the control register, respectively. if the on-chip reference is to be used externally in a system, it must be buffered before it is applied elsewhere. if an external reference is applied to the device, the internal reference is automatically overdriven. however, it is advised to disable the internal reference by setting the ref bit in the control register when an external reference is applied in order to obtain optimum performance from the device. when the internal reference is disabled, sw1, shown in figure 14 , opens and the input impedance seen at the ain1/v ref pin is the input impedance of the reference buffer, which is in the region of gigaohms. when the internal reference is enabled, the input impedance seen at the pin is typically 10 k. when the ad7887 is operated in two-channel mode, the reference is taken from v dd internally, not from the on-chip 2.5 v reference. 2.5v 10k ? sw1 ain1/v ref 06191-014 figure 14. on-chip reference circuitry
ad7887 rev. d | page 13 of 24 power-down options the ad7887 provides flexible power management to allow the user to achieve the best power performance for a given throughput rate. the power management options are selected by programming the power management bits (that is, pm1 and pm0) in the control register. table 6 summarizes the available options. when the power management bits are programmed for either of the auto power-down modes, the part enters power-down mode on the 16 th rising sclk edge after the falling edge of cs . the first falling sclk edge after the cs falling edge causes the part to power up again. when the ad7887 is in mode 1, that is, pm1 = pm0 = 0, the part enters shutdown on the rising edge of cs and power up from shutdown on the falling edge of cs . if cs is brought high during the conversion in this mode, the part immediately enters shutdown. power-up times the ad7887 has an approximate 1 s power-up time when powering up from standby or when using an external reference. when v dd is first connected the ad7887 powers up in mode 1, that is, pm1 = pm0 = 0. the part is put into shutdown on the rising edge of cs in this mode. a subsequent power-up from shutdown takes approximately 5 s. the ad7887 wake-up time is very short in the autostandby mode; therefore, it is possible to wake up the part and carry out a valid conversion in the same read/write operation. power vs. throughput rate by operating the ad7887 in autoshutdown mode, autostandby mode, or mode 1, the average power consumption of the ad7887 decreases at lower throughput rates. figure 15 shows how as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. for example, if the ad7887 is operated in a continuous sampling mode with a throughput rate of 10 ksps and a sclk of 2 mhz (v dd = 5 v), pm1 = 1 and pm0 = 0, that is, the device is in auto- shutdown mode, and the on-chip reference is used, the power consumption is calculated as follows: the power dissipation during normal operation is 3.5 mw (v dd = 5 v). if the power-up time is 5 s and the remaining conversion plus acquisition time is 15.5 t sclk , that is, approximately 7.75 s (see figure 18 ), the ad7887 can be said to dissipate 3.5 mw for 12.75 s during each conversion cycle. if the throughput rate is 10 ksps, the cycle time is 100 s and the average power dissipated during each cycle is (12.75/100) (3.5 mw) = 446.25 w. if v dd = 3 v, sclk = 2 mhz, and the device is in autoshutdown mode using the on-chip reference, the power dissipation during normal operation is 2.1 mw. the ad7887 can now be said to dissipate 2.1 mw for 12.75 s during each conversion cycle. with a throughput rate of 10 ksps, the average power dissipated during each cycle is (12.75/100) (2.1 mw) = 267.75 w. figure 15 shows the power vs. throughput rate for automatic shutdown with both 5 v and 3 v supplies. throughput rate (ksps) 10 0 power (mw) 1 10 0.1 0.01 v dd = 5v sclk = 2mhz v dd = 3v sclk = 2mhz 20 50 40 30 06191-015 figure 15. power vs. throughput rate modes of operation the ad7887 has several modes of operation that are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. the modes of operation are controlled by the pm1 and pm0 bits of the control register, as previously outlined in table 6 . for read-only operation of the ad7887, the default mode of all 0s in the control register can be set up by tying the din line permanently low. mode 1 (pm1 = 0, pm0 = 0) this mode allows the user to control the powering down of the part via the cs pin. whenever cs is low, the ad7887 is fully powered up; whenever cs is high, the ad7887 is in full shutdown. when cs goes from high to low, all on-chip circuitry starts to power up. it takes approximately 5 s for the ad7887 internal circuitry to be fully powered up. as a result, a conversion (or sample-and-hold acquisition) should not be initiated during this 5 s. figure 16 shows a general diagram of the operation of the ad7887 in this mode. the input signal is sampled on the second rising edge of sclk following the cs falling edge. the user should ensure that 5 s elapses between the falling edge of cs and the second rising edge of sclk. in microcontroller applications, this is readily achievable by driving the cs input from one of the port lines and ensuring that the serial data read (from the microcontrollers serial port) is not initiated for 5 s. in dsp applications, where cs is generally derived from the serial frame synchronization line, it is usually not possible to separate the cs falling edge and second sclk rising edge by up to 5 s without affecting the speed of the rest of the serial clock. therefore, the user must write to the control register to exit this mode and (by writing pm1 = 0 and pm0 = 1) put the part into mode 2, that is, normal mode. a second conversion needs to be initiated when the part is powered up to get a conversion result. the write operation that takes place in conjunction with this
ad7887 rev. d | page 14 of 24 second conversion can put the part back into mode 1, and the part goes into power-down mode when cs returns high. mode 2 (pm1 = 0, pm0 = 1) in this mode of operation, the ad7887 remains fully powered up regardless of the status of the cs line. it is intended for fastest throughput rate performance because the user does not have to worry about the 5 s power-up time previously mentioned. shows the general diagram of the operation of the ad7887 in this mode. figure 17 the data presented to the ad7887 on the din line during the first eight clock cycles of the data transfer are loaded to the control register. to continue to operate in this mode, the user must ensure that pm1 is loaded with 0 and pm0 is loaded with 1 on every data transfer. the falling edge of cs initiates the sequence, and the input signal is sampled on the second rising edge of the sclk input. sixteen serial clock cycles are required to complete the conversion and access the conversion result. once a data transfer is complete (that is, once cs returns high), another conversion can be initiated immediately by bringing cs low again. mode 3 (pm1 = 1, pm0 = 0) in this mode, the ad7887 automatically enters its full shutdown mode at the end of every conversion. it is similar to mode 1 except that the status of cs does not have any effect on the power-down status of the ad7887. figure 18 shows the general diagram of the operation of the ad7887 in this mode. on the first falling sclk edge after cs goes low, all on-chip circuitry starts to power up. it takes approximately 5 s for the ad7887 internal circuitry to be fully powered up. as a result, a conversion (or sample-and-hold acquisition) should not be initiated during this 5 s. the input signal is sampled on the second rising edge of sclk following the cs falling edge. the user should ensure that 5 s elapses between the first falling edge of sclk and the second rising edge of sclk after the cs falling edge, as shown in . in microcontroller applications (or with a slow serial clock), this is readily achievable by driving the figure 18 cs input from one of the port lines and ensuring that the serial data read (from the microcontrollers serial port) is not initiated for 5 s. however, for higher speed serial clocks, it will not be possible to have a 5 s delay between powering up and the first rising edge of the sclk. therefore, the user must write to the control register to exit this mode and (by writing pm1 = 0 and pm0 = 1) put the part into mode 2. a second conversion needs to be initiated when the part is powered up to get a conversion result, as shown in . the write operation that takes place in conjunction with this second conversion can put the part back into mode 3, and the part goes into power-down mode when the conversion sequence ends. figure 19 mode 4 (pm1 = 1, pm0 = 1) in this mode, the ad7887 automatically enters a standby (or sleep) mode at the end of every conversion. in this standby mode, all on-chip circuitry, apart from the on-chip reference, is powered down. this mode is similar to mode 3, but, in this case, the power-up time is much shorter because the on-chip reference remains powered up at all times. figure 20 shows the general diagram of the operation of the ad7887 in this mode. on the first falling sclk edge after cs goes low, the ad7887 comes out of standby. the ad7887 wake- up time is very short in this mode, so it is possible to wake up the part and carry out a valid conversion in the same read/write operation. the input signal is sampled on the second rising edge of sclk following the cs falling edge. at the end of conversion (last rising edge of sclk), the part automatically enters its standby mode.
ad7887 rev. d | page 15 of 24 sclk cs dout din 1 16 control register data is loaded on the first eight clocks. pm1 and pm0 = 0 to keep the part in this mode four leading zeros + conversion result data in the part powers up on cs falling edge as pm1 and pm0 = 0 the part powers down on cs rising edge as pm1 and pm0 = 0 0 6191-016 figure 16. mode 1 operation sclk cs dout din the part remains powered up at all times as pm1 = 0 and pm0 = 1 1 16 control register data is loaded on the first eight clocks. pm1 = 0 and pm0 = 1 to keep the part in this mode four leading zeros + conversion result data in 0 6191-017 figure 17. mode 2 operation
ad7887 rev. d | page 16 of 24 sclk cs dout din the part powers up from shutdown on sclk falling edge as pm1 = 1 and pm0 = 0 1 16 1 16 2 t 10 = 5s the part enters shutdown at the end of conversion as pm1 = 1 and pm0 = 0 control register data is loaded on the first eight clocks. pm1 = 1 and pm0 = 0 pm1 = 1 and pm0 = 0 to keep the part in this mode data in data in four leading zeros + conversion result four leading zeros + conversion result 0 6191-018 figure 18. mode 3 operation (microcontroller for slow sclks) sclk cs dout din 1 16 8 1 16 8 1 16 8 pm1 = 0 and pm0 = 1 to place the part in normal mode pm1 = 1 and pm0 = 0 to place the part back in mode 3 control register data is loaded on the first eight clocks. pm1 = 1 and pm0 = 0 the part enters shutdown at the end of conversion as pm1 = 1 and pm0 = 0 the part remains powered up as pm1 = 0 and pm0 = 1 the part begins to power up from shutdown the part enters shutdown at the end of conversion as pm1 = 1 and pm0 = 0 data in data in four leading zeros + conversion result four leading zeros + conversion result four leading zeros + conversion result data in 0 6191-019 figure 19. mode 3 operation (microcontroller for high speed sclks) sclk cs dout din control register data is loaded on the first eight clocks. pm1 = 1 and pm0 = 1 1 16 pm1 = 1 and pm0 = 1 to keep the part in this mode 1 16 the part powers up from standby on sclk falling edge as pm1 = 1 and pm0 = 1 the part enters standby at the end of conversion as pm1 = 1 and pm0 = 1 four leading zeros + conversion result data in four leading zeros + conversion result data in 0 6191-020 figure 20. mode 4 operation
ad7887 rev. d | page 17 of 24 serial interface figure 21 shows the detailed timing diagrams for serial interfacing to the ad7887. the serial clock provides the conversion clock and also controls the transfer of information to and from the ad7887 during conversion. cs initiates the data transfer and conversion process. for some modes, the falling edge of cs wakes up the part. in all cases, it gates the serial clock to the ad7887 and puts the on-chip track/hold into track mode. the input signal is sampled on the second rising edge of the sclk input after the falling edge of cs . thus, the first one and one-half clock cycles after the falling edge of cs are when the acquisition of the input signal takes place. this time is denoted as the acquisition time (t acq ). in modes where the falling edge of cs wakes up the part, the acquisition time must allow for the wake-up time of 5 s. the on-chip track/hold goes from track mode to hold mode on the second rising edge of sclk, and a conversion is also initiated on this edge. the conversion process takes an additional fourteen and one-half sclk cycles to complete. the rising edge of cs puts the bus back into three-state. if cs is left low, a new conversion can be initiated. in dual-channel operation, the input channel that is sampled is the one that was selected in the previous write to the control register. thus, in dual-channel operation, the user must write the channel address for the next conversion while the present conversion is in progress. writing of information to the control register takes place on the first eight rising edges of sclk in a data transfer. the control register is always written to when a data transfer takes place. however, the ad7887 can be operated in a read-only mode by tying din low, thereby loading all 0s to the control register every time. when operating the ad7887 in write/read mode, the user must be careful to always set up the correct information on the din line when reading data from the part. sixteen serial clock cycles are required to perform the con- version process and to access data from the ad7887. in applications where the first serial clock edge following cs going low is a falling edge, this edge clocks out the first leading zero. thus, the first rising clock edge on the sclk clock has the first leading zero provided. in applications where the first serial clock edge following cs going low is a rising edge, the first leading zero may not be set up in time for the processor to read it correctly. however, subsequent bits are clocked out on the falling edge of sclk so that they are provided to the processor on the following rising edge. thus, the second leading zero is clocked out on the falling edge subsequent to the first rising edge. the final bit in the data transfer is valid on the 16 th rising edge, having been clocked out on the previous falling edge. dontc zero zero 0mp 1mp hclaud/nisfer sclk 6 5 1 15 dout din 234 16 t 1 t acq t convert t 2 t 6 t 7 t 3 t 8 db11 db0 db10 db9 three- state four leading zeros cs three- state t 4 t 5 06191-021 figure 21. serial interface timing diagram
ad7887 rev. d | page 18 of 24 microprocessor interfacing the serial interface on the ad7887 allows the part to be directly connected to a range of many different microprocessors. this section explains how to interface the ad7887 with some of the more common microcontroller and dsp serial interface protocols. ad7887 to tms320c5x the serial interface on the tms320c5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7887. the cs input allows easy interfacing with an inverter between the serial clock of the tms320c5x and the ad7887 being the only glue logic required. the serial port of the tms320c5x is set up to operate in burst mode with internal clkx (tx serial clock) and fsx (tx frame sync). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1, and txm = 1. the connection diagram is shown in . figure 22 ad7887 1 dout din sclk cs tms320c5x 1 1 additional pins omitted for clarity. clkx clkr dr dt fsx fsr 06191-022 figure 22. interfacing to the tms320c5x ad7887 to adsp-21xx the adsp-21xx family of dsps are easily interfaced to the ad7887 with an inverter between the serial clock of the adsp- 21xx and the ad7887. this is the only glue logic required. the sport control register should be set up as follows: table 7. sport0 control register setup setting description tfsw = rfsw = 1 alternative framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data slen = 1111 16-bit data-word isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word irfs = 0 itfs = 1 the connection diagram is shown in figure 23 . the adsp-21xx has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode, and the sport control register is set up as described in table 7 . the frame synchronization signal generated on the tfs is tied to cs and, as with all signal processing applications, equidistant sampling is necessary. in this example however, the timer interrupt is used to control the sampling rate of the adc and, under certain conditions, equidistant sampling cannot be achieved. the timer registers are loaded with a value that will provide an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and hence the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given (that is, ax0 = tx0), the state of the sclk is checked. the dsp waits until the sclk has gone high, low, and high again before a transmission starts. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, the data may be transmitted or it may wait until the next clock edge. for example, the adsp-2111 has a master clock frequency of 16 mhz. if the sclkdiv register is loaded with the value 3, a sclk of 2 mhz is obtained and eight master clock periods will elapse for every one sclk period. if the timer registers are loaded with the value 803, 100.5 sclks will occur between interrupts and subsequently between transmit instructions. this situation results in nonequidistant sampling because the transmit instruction is occurring on an sclk edge. if the number of sclks between interrupts is a whole integer number of n, equidistant sampling will be implemented by the dsp. ad7887 1 dout din sclk cs 1 additional pins omitted for clarity. sclk dr dt rfs tfs adsp-21xx 1 06191-023 figure 23. interfacing to the adsp-21xx ad7887 to dsp56xxx the connection diagram in figure 24 shows how the ad7887 can be connected to the ssi (synchronous serial interface) of the dsp56xxx family of dsps from motorola. the ssi is operated in synchronous mode (syn bit in crb = 1) with an internally generated 1-bit clock period frame sync for both tx and rx (bits fsl1 = 1 and fsl0 = 0 in crb). set the word length to 16 by setting bits wl1 = 1 and wl0 = 0 in cra. an inverter is also necessary between the sclk from the dsp56xxx and the sclk pin of the ad7887, as shown in figure 24 . dout din sclk cs 1 additional pins omitted for clarity. dsp56xxx 1 ad7887 1 sck srd std sc2 0 6191-024 figure 24. interfacing to the dsp56xxx
ad7887 rev. d | page 19 of 24 dout din sclk cs 1 additional pins omitted for clarity. ad7887 1 8051 1 p1.3 p1.0 p1.1 p1.2 06191-026 ad7887 to mc68hc11 the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1) when the clock polarity bit (cpol) = 1 and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)see the m68hc11 reference manual from freescale semiconductor, inc., for more information. the serial transfer takes place as two 8-bit operations. a connection diagram is shown in figure 25 . figure 26. interfacing to the 8051 using input/output ports ad7887 to pic16c6x/pic16c7x dout din sclk cs 1 additional pins omitted for clarity. mc68hc11 1 ad7887 1 sclk/pd4 miso/pd2 mosi/pd3 pa0 0 6191-025 the pic16c6x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit = 1. this is done by writing to the synchronous serial port control register (sspcon). see the pic16/pic17 microcontroller user manual . figure 27 shows the hardware connections needed to interface to the pic16c6x/ pic16c7x. in this example, input/output port ra1 is being used to pulse cs . this microcontroller only transfers eight bits of data during each serial transfer operation. therefore, two consecutive read/write operations are needed. figure 25. interfacing to the mc68hc11 ad7887 to 8051 dout din sclk cs 1 additional pins omitted for clarity. ad7887 1 pic16c6x/ pic16c7x 1 sck/rc3 sdo/rc5 ra1 sdi/rc4 06191-027 it is possible to implement a serial interface using the data ports on the 8051. this allows a full duplex serial transfer to be imple- mented. the technique involves bit-banging an input/output port (for example, p1.0) to generate a serial clock and using two other input/output ports (for example, p1.1 and p1.2) to shift data in and outsee figure 26 . figure 27. interfacing to the pic16c6x/pic16c7x
ad7887 rev. d | page 20 of 24 application hints grounding and layout the ad7887 has very good immunity to noise on the power supplies, as can be seen in figure 7 . however, care should still be taken with regard to grounding and layout. the printed circuit board that houses the ad7887 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes because it results in the best shielding. digital and analog ground planes should be joined in only one place, as close as possible to the gnd pin of the ad7887. if the ad7887 is in a system where multiple devices require agnd-to-dgnd connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the ad7887. avoid running digital lines under the device because these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7887 to avoid noise coupling. the power supply lines to the ad7887 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best approach, but it is not always possible with a double- sided board. in this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantal um in parallel with 0.1 f capacitors to agnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. evaluating the ad7887 performance the recommended layout for the ad7887 is outlined in the evaluation board for the ad7887. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the eval-control board. the eval-control board can be used in conjunction with the ad7887 evaluation board, as well as many other analog devices, inc., evaluation boards ending in the cb designator, to demonstrate/evaluate the ac and dc performance of the ad7887. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7887.
ad7887 rev. d | page 21 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 060506-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 28. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) figure 29. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model linearity error 1 temperature package description package option branding ad7887ar 2 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887ar-reel 2 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887ar-reel7 2 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887arz 2 2 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887arz-reel 2 2 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887arz-reel7 2 2 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887arm 2 lsb ?40c to +125c 8-lead mini small outline package [msop] rm-8 c5a ad7887arm-reel 2 lsb ?40c to +125c 8-lead mini small outline package [msop] rm-8 c5a ad7887arm-reel7 2 lsb ?40c to +125c 8-lead mini small outline package [msop] rm-8 c5a ad7887armz 2 2 lsb ?40c to +125c 8-lead mini small outline package [msop] rm-8 c5a# ad7887armz-reel 2 2 lsb ?40c to +125c 8-lead mini small outline package [msop] rm-8 c5a# ad7887armz-reel7 2 2 lsb ?40c to +125c 8-lead mini small outline package [msop] rm-8 c5a# ad7887br 1 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887br-reel 1 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887br-reel7 1 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887brz 2 1 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887brz-reel 2 1 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ad7887brz-reel7 2 1 lsb ?40c to +125c 8-lead standard small outline package [soic_n] r-8 2 lsb ?40c to +125c 8-lead mini small outline package [msop] rm-8 c5a# ad7887warmz 2 , 3 eval-ad7887cb 4 evaluation board eval-control brd2 5 controller board 1 linearity error here refers to integral linearity error. 2 z = rohs compliant part, # denotes lead-free product, may be top or bottom marked. 3 qualified for automotive. 4 this can be used as a standalone evaluation board or can be used in conjunction with the eval-control board for evaluation/dem onstration purposes. 5 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designator.
ad7887 rev. d | page 22 of 24 notes
ad7887 rev. d | page 23 of 24 notes
ad7887 rev. d | page 24 of 24 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06191-0-2/09(d)

▲Up To Search▲

Price & Availability of EVAL-AD7887CB4

	To Download EVAL-AD7887CB4 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .